By way of example, the present is particularly well suited (though not exclusively) to an architecture for distributing supply voltages to a plurality of Flash memory modules. The following description is provided with reference to this field of application for clarity of illustration only.
A Flash non-volatile memory requires a plurality of voltages, which are generated from a same supply voltage reference Vdd. In particular, to correctly perform the different operations (reading, programming, and erasing) on Flash memory cells, some voltages among the plurality of voltages need to have a higher value than the supply voltage Vdd, while other voltages need to have negative values. That is, these are values lower than a ground voltage reference GND, corresponding to a zero or null voltage value.
To increase memory performance, the memory may be split into several banks or modules, and the above-noted operations (i.e., reading, programming, and erasing) are performed in parallel on different banks. Memory architectures capable of performing a reading operation on different banks are known in the art. Examples of such memory architectures are described in U.S. Pat. Nos. 5,691,955 (assigned to Mitsubishi Electric) and 5,684,752 (assigned to Intel).
Memory architectures capable of performing reading and programming operations in parallel are also known, and examples thereof are described in U.S. Pat. Nos. 5,245,572 (assigned to Intel) and 5,867,430 to Chen et al., for example. The memory architecture described in the Chen et al. patent is also capable of performing reading and erasing operations in parallel as well.
Such architectures may have certain limitations. First, it may not be possible to perform programming and erasing operations in parallel. Moreover, these architectures are not capable of managing more than two parallel operations. Additionally, these architectures are not capable of managing requests from a number of banks that is different from the number contemplated during the design of the architecture, unless the hardware structure of the architecture itself is changed.